1. Field of the Invention
The present invention relates to an apparatus for correcting errors of digital data and, more particularly, to an error correcting apparatus suitable for use in the reproducing section of a digital video tape recorder.
2. Description of the Background
There are now known video tape recorders for digitally recording/reproducing a video signal (hereinafter simply referred to as digital VTR) in which investigations have been made relating to use of the product code as an error correction code that would be effective for correcting burst errors, which are due to signal dropout caused by tape defects or the like. This product code involves manipulation of the data arranged as the inner code in the lateral or horizontal direction and the outer code in the vertical direction for data arranged two-dimensionally. This is, of course, an abstract concept and the data is not physically arranged two dimensionally, only the addresses are based on a two-dimensional array. Inner and outer are used in place of vertical and horizontal because they make the concepts involved easier to visualize.
In the recording system of a digital VTR that uses the product code for error correction, the outer code is encoded with respect to the input digital video signal consisting of data symbols, which are obtained by analog-to-digital (A/D) converting an input analog video signal. Next, the inner code is encoded with regard to the input data symbols and the parity symbols of the outer code.
Further, those symbols are shuffled, and the input digital video signal is recorded on a magnetic tape by rotary heads in the shuffled state. Therefore, each symbol of the digital video data is effectively encoded twice, based on both the outer code and the inner code.
A code that may be used as the outer and inner codes is the Reed-Solomon code, for example, in which two parity symbols are reproduced for every respective error correction code block. With this Reed-Solomon code, a one-symbol error in a code block can be corrected and the two-symbol error can be erasure corrected.
In the reproducing system of a digital VTR, the digital signal reproduced from the magnetic tape by the rotary heads is first decoded by an inner code decoder and, because the time sequence of the reproduced data coincides with the sequence of the data series of the inner code, there is no need to rearrange the data in this decoder of the inner code.
The reproduced data whose errors were corrected by the inner code decoder is then supplied to the rearrangement circuit or shuffling circuit, in which the time sequence of the data is converted into the sequence of the outer code and further decoded by the decoder of the outer code, when in the standard reproducing mode. More specifically, (m+2) symbols at the respective first positions are selected from the respective blocks of the inner codes, which are located in the vertical direction in the inner code blocks, for example, the inner code blocks of [1, 1], [2, 1], . . . , [(m+1), 1], and [(m+2), 1]. These (m+2) symbols are supplied to a syndrome producing circuit of the outer code decoder, so that the syndromes of the blocks of the outer code are produced. In a manner similar to the inner codes, the data is rearranged and (m+2) symbols at the respective last (ith) positions are selected from the respective blocks of the inner codes of [1, n], [2, n], . . . , [(m+1), n], and
[(m+2), n], so that the syndromes of the outer code blocks are produced.
The rearrangement circuit to execute the foregoing data rearrangement comprises a memory that must have a memory capacity that is sufficient to completely store all of the blocks [n.times.(m+2)] of the inner codes.
The decoder of the outer code is constituted by the syndrome producing circuit, a correction operation circuit, a data delay circuit, and an error correcting circuit. The syndromes of the outer code, are calculated by the syndrome producing circuit. Two syndromes are produced in the case of using the Reed-Solomon code of two parity symbols in the outer code block, and the sizes of the errors are calculated. An output of the correction operating circuit and the output data of the data delay circuit are supplied to the error correcting circuit. The resultant error is modulo-2 added at the position of the error symbol in the reproduced data from the data delay circuit, and the requisite error correction is carried out. The data delay circuit is used for phase matching between the output of the correction operating circuit and the reproduced data and provides the delay amount of (m+2) symbols.
Thus, the digital data output, which was respectively subjected to the error correcting processes using the inner code and outer code, is obtained from the decoder of the outer code.
In the variable speed reproducing mode, such as the high-speed reproducing mode, low-speed reproducing mode, still mode, or the like, the angle of inclination of the tracks formed on the magnetic tape does not coincide with the angle of inclination of the scan track of the rotary heads, so that the data is intermittently reproduced. Therefore, all of the data that forms the code block of the outer code can not be obtained in these nonstandard reproduction modes. Thus, in such known systems the data is transferred by bypassing the decoder of the outer code and the outer code is not decoded. Only that data, which was determined to have no error, based only on the inner code is written into a buffer memory having a large capacity, for example, a memory capacity large enough to store the digital data of three complete fields.
The data writing operation into the buffer memory is executed in accordance with the block addresses added for every two inner code blocks, and the data of the same field that is among the data that was intermittently stored is collectively outputted from the buffer memory.
The output data read out from the buffer memory is then supplied to the rearranging or deshuffling circuit, in order to return the sequence of the data series to the original sequence. More specifically, the deshuffling circuit performs data rearrangement exactly opposite to that of the shuffling circuit provided in the recording circuit. By recording the data in the shuffled state and then deshuffling the data upon reproduction the concentration of errors to one location is prevented. The memory capacity of the deshuffling circuit is determined in correspondence to the length of unit of the shuffling that was performed.
The output of the deshuffling circuit is supplied to an error concealment circuit to conceal errors that can not be corrected. The error concealment circuit interpolate the erroneous sampling data by using the correct sampling data located around this error sampling data. An output of the error concealment circuit is supplied to a digital-to-analog (D/A) converter and the reproduced analog video signal is obtained from its output terminal.
The above-mentioned conventional apparatus for decoding the error correction code has several drawbacks, one of which is that a memory having an extremely large capacity is needed for the rearrangement from the inner code sequence to the outer code sequence in the outer code decoder. In addition, a memory of capacity corresponding to the unit length of the shuffling operation is also necessary in the deshuffling circuit.
In the slow-motion reproducing operation, in particular in the variable speed reproducing operations, the data of one complete unit of the product code is not quite reproduced for the interval of a plurality of fields. However, the conventional decoding apparatus cannot decode the outer code in such a slow-motion reproducing operation.
Furthermore, since intermittent data is reproduced in the variable speed reproducing mode, in the case where the current reproduced data is written into the buffer memory and this data is then read out, the data which has already been read out frequently remains in the buffer memory without being updated, and such old data causes the reproduced picture quality to deteriorate.
To avoid this problem, a flag memory is provided with the same address as that supplied to the buffer memory and after the data has been read out from the buffer memory, an error flag indicative of old data is immediately written into the address of the flag memory read out. This error flag is used to distinguish the reproduced new-data (New) from the reproduced old-data (Old) and referred to as a New/Old (N/O) flag. Among the data read out from the buffer memory, the data that has been determined to be the old-data (Old) by the N/O flag is concealed by the error concealment circuit in the following stage.
On the other hand, even when considering such a system in which a buffer memory is arranged between the decoder of the inner code and the decoder of the outer code there is also at least the following drawback. As in the conventional apparatus, if writing data into the buffer memory is inhibited when the error data remains, as the result of the decoding of the inner code, even in the case where only a part of the data in the code block of the inner code is error data, the whole code block is not written, so that the error correcting capability of the outer code cannot be sufficiently used.
In the digital VTR of the segment system, for example, assuming that the reproducing speed of the tape is 1/2 of the recording speed of the tape, a period of time which is twice as long as the ordinary reproducing mode is required to reproduce the video data of one field. The time period for writing the data into a field memory of the buffer memory is also twice as long as that in the ordinary writing mode. Therefore, it is impossible to read out and use the video data from this field memory, so the old data of one field that was written in the other field memory is read out twice. In this manner, in the case of repeatedly reading out the data from the buffer memory for two fields, the conventional N/O flag indicates that all of the readout data is the old data with respect to the video data read out the second time. Consequently, all of the video data of one field read out at the second time must be error corrected. Such error correction is obviously impossible, and the conventional method of forming the N/O flag is very inconvenient in the slow motion reproducing operation of the digital VTR.